/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'cpu' in SOPC Builder design 'NiosII'
 * SOPC Builder design path: C:/Users/maoxiang/Desktop/NiosIITemplate/NiosII.sopcinfo
 *
 * Generated: Wed May 25 18:50:13 CST 2016
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * BUS configuration
 *
 */

#define ALT_MODULE_CLASS_BUS bus
#define BUS_BASE 0x40000
#define BUS_IRQ -1
#define BUS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BUS_NAME "/dev/BUS"
#define BUS_SPAN 262144
#define BUS_TYPE "bus"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x1020
#define ALT_CPU_CPU_FREQ 100000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x19
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x1800020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 100000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INST_ADDR_WIDTH 0x19
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_RESET_ADDR 0x0


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x1020
#define NIOS2_CPU_FREQ 100000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x19
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x1800020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INST_ADDR_WIDTH 0x19
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_RESET_ADDR 0x0


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_NIOS2_QSYS
#define __BUS
#define __CHARGE
#define __DDS_AM_INTERFACE
#define __DDS_FM_INTERFACE
#define __DDS_SINE_INTERFACE
#define __KEY4X4


/*
 * EPCS configuration
 *
 */

#define ALT_MODULE_CLASS_EPCS altera_avalon_epcs_flash_controller
#define EPCS_BASE 0x0
#define EPCS_IRQ 1
#define EPCS_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCS_NAME "/dev/EPCS"
#define EPCS_REGISTER_OFFSET 1024
#define EPCS_SPAN 2048
#define EPCS_TYPE "altera_avalon_epcs_flash_controller"


/*
 * KEY4X4IRQ configuration
 *
 */

#define ALT_MODULE_CLASS_KEY4X4IRQ altera_avalon_pio
#define KEY4X4IRQ_BASE 0x1870
#define KEY4X4IRQ_BIT_CLEARING_EDGE_REGISTER 0
#define KEY4X4IRQ_BIT_MODIFYING_OUTPUT_REGISTER 0
#define KEY4X4IRQ_CAPTURE 1
#define KEY4X4IRQ_DATA_WIDTH 1
#define KEY4X4IRQ_DO_TEST_BENCH_WIRING 0
#define KEY4X4IRQ_DRIVEN_SIM_VALUE 0
#define KEY4X4IRQ_EDGE_TYPE "RISING"
#define KEY4X4IRQ_FREQ 100000000
#define KEY4X4IRQ_HAS_IN 1
#define KEY4X4IRQ_HAS_OUT 0
#define KEY4X4IRQ_HAS_TRI 0
#define KEY4X4IRQ_IRQ 2
#define KEY4X4IRQ_IRQ_INTERRUPT_CONTROLLER_ID 0
#define KEY4X4IRQ_IRQ_TYPE "EDGE"
#define KEY4X4IRQ_NAME "/dev/KEY4X4IRQ"
#define KEY4X4IRQ_RESET_VALUE 0
#define KEY4X4IRQ_SPAN 16
#define KEY4X4IRQ_TYPE "altera_avalon_pio"


/*
 * Key4x4 configuration
 *
 */

#define ALT_MODULE_CLASS_Key4x4 Key4x4
#define KEY4X4_BASE 0x1898
#define KEY4X4_IRQ -1
#define KEY4X4_IRQ_INTERRUPT_CONTROLLER_ID -1
#define KEY4X4_NAME "/dev/Key4x4"
#define KEY4X4_SPAN 1
#define KEY4X4_TYPE "Key4x4"


/*
 * LCD12864RS configuration
 *
 */

#define ALT_MODULE_CLASS_LCD12864RS altera_avalon_pio
#define LCD12864RS_BASE 0x1860
#define LCD12864RS_BIT_CLEARING_EDGE_REGISTER 0
#define LCD12864RS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD12864RS_CAPTURE 0
#define LCD12864RS_DATA_WIDTH 1
#define LCD12864RS_DO_TEST_BENCH_WIRING 0
#define LCD12864RS_DRIVEN_SIM_VALUE 0
#define LCD12864RS_EDGE_TYPE "NONE"
#define LCD12864RS_FREQ 100000000
#define LCD12864RS_HAS_IN 0
#define LCD12864RS_HAS_OUT 1
#define LCD12864RS_HAS_TRI 0
#define LCD12864RS_IRQ -1
#define LCD12864RS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LCD12864RS_IRQ_TYPE "NONE"
#define LCD12864RS_NAME "/dev/LCD12864RS"
#define LCD12864RS_RESET_VALUE 0
#define LCD12864RS_SPAN 16
#define LCD12864RS_TYPE "altera_avalon_pio"


/*
 * LCD12864RST configuration
 *
 */

#define ALT_MODULE_CLASS_LCD12864RST altera_avalon_pio
#define LCD12864RST_BASE 0x1850
#define LCD12864RST_BIT_CLEARING_EDGE_REGISTER 0
#define LCD12864RST_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCD12864RST_CAPTURE 0
#define LCD12864RST_DATA_WIDTH 1
#define LCD12864RST_DO_TEST_BENCH_WIRING 0
#define LCD12864RST_DRIVEN_SIM_VALUE 0
#define LCD12864RST_EDGE_TYPE "NONE"
#define LCD12864RST_FREQ 100000000
#define LCD12864RST_HAS_IN 0
#define LCD12864RST_HAS_OUT 1
#define LCD12864RST_HAS_TRI 0
#define LCD12864RST_IRQ -1
#define LCD12864RST_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LCD12864RST_IRQ_TYPE "NONE"
#define LCD12864RST_NAME "/dev/LCD12864RST"
#define LCD12864RST_RESET_VALUE 0
#define LCD12864RST_SPAN 16
#define LCD12864RST_TYPE "altera_avalon_pio"


/*
 * LCDLEDA configuration
 *
 */

#define ALT_MODULE_CLASS_LCDLEDA altera_avalon_pio
#define LCDLEDA_BASE 0x1840
#define LCDLEDA_BIT_CLEARING_EDGE_REGISTER 0
#define LCDLEDA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LCDLEDA_CAPTURE 0
#define LCDLEDA_DATA_WIDTH 1
#define LCDLEDA_DO_TEST_BENCH_WIRING 0
#define LCDLEDA_DRIVEN_SIM_VALUE 0
#define LCDLEDA_EDGE_TYPE "NONE"
#define LCDLEDA_FREQ 100000000
#define LCDLEDA_HAS_IN 0
#define LCDLEDA_HAS_OUT 1
#define LCDLEDA_HAS_TRI 0
#define LCDLEDA_IRQ -1
#define LCDLEDA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LCDLEDA_IRQ_TYPE "NONE"
#define LCDLEDA_NAME "/dev/LCDLEDA"
#define LCDLEDA_RESET_VALUE 0
#define LCDLEDA_SPAN 16
#define LCDLEDA_TYPE "altera_avalon_pio"


/*
 * LCDSPI configuration
 *
 */

#define ALT_MODULE_CLASS_LCDSPI altera_avalon_spi
#define LCDSPI_BASE 0x1800
#define LCDSPI_CLOCKMULT 1
#define LCDSPI_CLOCKPHASE 0
#define LCDSPI_CLOCKPOLARITY 1
#define LCDSPI_CLOCKUNITS "Hz"
#define LCDSPI_DATABITS 8
#define LCDSPI_DATAWIDTH 16
#define LCDSPI_DELAYMULT "1.0E-9"
#define LCDSPI_DELAYUNITS "ns"
#define LCDSPI_EXTRADELAY 0
#define LCDSPI_INSERT_SYNC 0
#define LCDSPI_IRQ 3
#define LCDSPI_IRQ_INTERRUPT_CONTROLLER_ID 0
#define LCDSPI_ISMASTER 1
#define LCDSPI_LSBFIRST 0
#define LCDSPI_NAME "/dev/LCDSPI"
#define LCDSPI_NUMSLAVES 1
#define LCDSPI_PREFIX "spi_"
#define LCDSPI_SPAN 32
#define LCDSPI_SYNC_REG_DEPTH 2
#define LCDSPI_TARGETCLOCK 8000000u
#define LCDSPI_TARGETSSDELAY "0.0"
#define LCDSPI_TYPE "altera_avalon_spi"


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone IV E"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x1042008
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x1042008
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x1042008
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "NiosII"


/*
 * charge configuration
 *
 */

#define ALT_MODULE_CLASS_charge charge
#define CHARGE_BASE 0x1888
#define CHARGE_IRQ -1
#define CHARGE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define CHARGE_NAME "/dev/charge"
#define CHARGE_SPAN 8
#define CHARGE_TYPE "charge"


/*
 * dds_AM_interface configuration
 *
 */

#define ALT_MODULE_CLASS_dds_AM_interface dds_AM_interface
#define DDS_AM_INTERFACE_BASE 0x1830
#define DDS_AM_INTERFACE_IRQ -1
#define DDS_AM_INTERFACE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DDS_AM_INTERFACE_NAME "/dev/dds_AM_interface"
#define DDS_AM_INTERFACE_SPAN 16
#define DDS_AM_INTERFACE_TYPE "dds_AM_interface"


/*
 * dds_FM_interface configuration
 *
 */

#define ALT_MODULE_CLASS_dds_FM_interface dds_FM_interface
#define DDS_FM_INTERFACE_BASE 0x1820
#define DDS_FM_INTERFACE_IRQ -1
#define DDS_FM_INTERFACE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DDS_FM_INTERFACE_NAME "/dev/dds_FM_interface"
#define DDS_FM_INTERFACE_SPAN 16
#define DDS_FM_INTERFACE_TYPE "dds_FM_interface"


/*
 * dds_sine_interface configuration
 *
 */

#define ALT_MODULE_CLASS_dds_sine_interface dds_sine_interface
#define DDS_SINE_INTERFACE_BASE 0x1880
#define DDS_SINE_INTERFACE_IRQ -1
#define DDS_SINE_INTERFACE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DDS_SINE_INTERFACE_NAME "/dev/dds_sine_interface"
#define DDS_SINE_INTERFACE_SPAN 8
#define DDS_SINE_INTERFACE_TYPE "dds_sine_interface"


/*
 * hal configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none


/*
 * jtag_uart_0 configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x1042008
#define JTAG_UART_0_IRQ 0
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8


/*
 * sdram configuration
 *
 */

#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller
#define SDRAM_BASE 0x1800000
#define SDRAM_CAS_LATENCY 3
#define SDRAM_CONTENTS_INFO
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_IRQ -1
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_NAME "/dev/sdram"
#define SDRAM_POWERUP_DELAY 100.0
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SDRAM_ADDR_WIDTH 0x16
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SHARED_DATA 0
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SPAN 8388608
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_T_AC 5.5
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20.0
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_WR 14.0


/*
 * sysid_qsys_0 configuration
 *
 */

#define ALT_MODULE_CLASS_sysid_qsys_0 altera_avalon_sysid_qsys
#define SYSID_QSYS_0_BASE 0x1890
#define SYSID_QSYS_0_ID 0
#define SYSID_QSYS_0_IRQ -1
#define SYSID_QSYS_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_QSYS_0_NAME "/dev/sysid_qsys_0"
#define SYSID_QSYS_0_SPAN 8
#define SYSID_QSYS_0_TIMESTAMP 1464146164
#define SYSID_QSYS_0_TYPE "altera_avalon_sysid_qsys"

#endif /* __SYSTEM_H_ */
